A. Technical Field
The present invention relates to the field of electronics and data communication, and more particularly, to systems, devices and methods of employing an internal frequency synthesizer to generate high frequency oversampling clocks adaptive to predetermined parameters, such as a bit depth and an oversampling rate, for a serial data interface.
B. Background of the Invention
A large amount of signals are transmitted between different components in an embedded hardware system, and to maintain high efficiency, the signals have to be coordinated using a specific signal transmission standard. The Serial Peripheral Interface (SPI) is a generic standard applicable to most embedded systems. It is a synchronous serial data link standard which connects a master device and its slave devices through four standard logic signals, serial clock (SCLK), data in (DIN), data out (DO) and slave select (SS). Input serial data are synchronized with the input serial clock and converted to parallel control outputs in the slave devices under the control of the slave select. The data are returned from the selected slave device as a serial digital signal or as an analog signal, and thus, only one output pin is needed for the master device to receive the outcome. As the parallel-to-serial and serial-to-parallel data shifting techniques mature, the use of the Serial Peripheral Interface allows tremendous pin count reduction and board real estate saving while consuming only limited chip area for data shifting. Nowadays, the Serial Peripheral Interfaces are used in microprocessors, microcontrollers and their peripherals such as sensors, actuators, cameras, memory arrays and displays.
In many digital audio systems, the Serial Peripheral Interface may be further simplified to a three-signal Integrated Interchip Sound (I2S) interface. These audio systems normally include audio media (tape, compact disc or digital TV sound) and a number of processing circuits comprising analog-to-digital converters (ADCs), digital-to-analog converters (DACs), error correction circuit, digital filters and interface electronics. The data out signal in the SPI is also needed in the I2S interface when returned data are involved in some audio applications, such as audio ADCs. The slave select signal in the SPI is converted to a low frequency left/right clock (LRCLK), which is also called as word select (WS). In a stereo system, the left/right clock multiplexes two audio channels through its logic levels in the time domain. The audio information is stored in the data in (DIN) signal and the DIN signal is synchronized with the serial clock (SCLK) which is often called as bit clock (BCLK) in audio applications. Most audio systems function under the control of such a three- or four-signal I2S interface comprising the bit clock, the left/right clock and the serial data in and/or serial data out.
The SPI interface and the I2S interface meet data communication requirements in most embedded and audio systems; however, additional high frequency clock signals may be required in some applications. For example, A/D and D/A converters in many audio systems involve sigma-delta (Σ-Δ) modulation and a high frequency master clock (MCLK) is required for oversampling in A/D or D/A conversion. The frequency of the master clock is an integer multiple, typically 128, of the left/right clock frequency. This ratio of the MCLK/LRCLK is also referred to as the oversampling rate. The master clock is used to generate an oversampling clock, and therefore, the jitter noise of the master clock has to be low enough to avoid degrading the audio quality. Constrained by such a low jitter requirement, the A/D and D/A converters in prior arts rely on external master clock signals. However, the incoming master clock is required to synchronize with the I2S interface, and the drive circuit of the master clock may dominate power consumption in the input/output (I/O) interface and potentially causes electromagnetic interferences or compatibility (EMI/EMC) issues. The master clock provided externally is not a preferred solution for a low-power low-cost device.
Data transmission using serial data interfaces has significantly reduced the pin count for integrated circuit components. However, additional pin count reduction is highly desirable in order to further simply system integration and enhance cost efficiency. The prior arts in some audio applications reduce the pin count by regenerating the bit clock from the master clock using digital dividers. The aforementioned issue of power consumption still exists. Data clock synchronization becomes another challenge and may impose unexpected constraints on clock timing.